The invention relates generally to a Controlled Area Network and more particularly to a receiving circuit and method for such a network.
A Controlled Area Network (CAN) system is provided for motor vehicles and comprises a plurality of transmitters and receivers interconnected via a bus line system. This allows control systems, sensors, measurement transducers and receivers, control signal receivers, actuating means etc. to be linked to each other.
For reasons of safety, a preferred CAN system performs a digital data transfer via a double-line bus having two lines, with the pulse signals to be transmitted being transmitted simultaneously via both lines and being synchronous in terms of pulse times and pulse length thereof, but opposite in terms of logic value. This provides a transfer redundance ensuring an error-free data transfer also in case of numerous error conditions of the bus system. Such errors are line interruptions, line short circuits towards battery voltage or ground and mutual short circuits between the two lines of the double-line bus.
A known receiving circuit comprising such a double-line bus system is known, for example, in the form of integrated circuit PCA82C252 of Philips. FIG. 6 shows in a block diagram the essential components of this known receiving circuit of interest here. The known circuit comprises two terminals for connection to a first line CANH and for connection to a second line CANL of the double-line bus, respectively. CANH is connected to a non-inverting input of a comparator COMP1 via an offset voltage source Voffset, and CANL is connected directly to an inverting input of comparator COMP1. Voffset superimposes an offset voltage of +2.8V on the pulse signal received via CANH. The pulse signal received via CANH furthermore is fed to non-inverting inputs of comparators COMPS2 and COM4. The pulse signal received via CANL is fed to a non-inverting input of a comparator COMP3 and to an inverting input of a comparator COMP5. The inverting inputs of COMP2 and COMP3 are connected to a reference voltage source REF1 supplying to these inverting inputs a reference voltage of +5V. By means of a reference voltage source REF2, a reference voltage of +2.8V is fed to the inverting input of COMP4 and to the non-inverting input of COMP5.
The outputs of comparators COMP1, COMP4 and COMP5 are connected to three different inputs of a switching means SW connected on its output side to an output terminal RxD of the receiving circuit. Switching over of switching means SW is controlled by a multiplex control logic circuit MUX comprising a first input E1 connected to the output of COMP2, a second input E2 connected to the output of COMP3 and a third input E3. E3 is connected to the input of a timer T having its input connected to the output side of switching means SW.
The mode of operation of this known receiving circuit will now be elucidated with the aid of FIGS. 7 to 9. Eight possible modes of operation will be considered depending on the condition of the double-line bus, namely:
case 1: lines CANH and CANL operate properly
case 2: line CANH is interrupted
case 3: line CANL is interrupted
case 4: line CANH is short circuited to battery
case 5: line CANL is short circuited to ground
case 6: line CANH is short circuited to ground
case 7: line CANL is short circuited to battery
case 8: lines CANL and CANH are short circuited to each other.
The mode of operation of the receiving circuit will now be discussed briefly for these cases. FIGS. 7 to 9 each show the pulse signal on CANL, the pulse signal on CANH, and in broken lines the pulse signal of CANH increased by +Voffset, and the output signal of the receiving circuit arising at RxD. For the sake of brevity and simplicity, the individual signals are designated only with the names of the associated lines and terminals, respectively.
The mode of operation of the known receiving circuit according to FIG. 6 will now be elucidated briefly with respect to the eight cases indicated.
Case 1
The associated signal paths are shown in FIG. 7. As soon as the potential of CANL reaches the value of CANH+Voffset, the output signal of the receiving circuit changes from a high to a low logic value. When CANL thereafter drops again below CANH+Voffset, the output of the receiving circuit changes from a low to a high logic value. The data content contained in CANH thus is reflected on the output of the receiving circuit.
Case 2
When line CANH is interrupted, a low logic value appears at the corresponding input terminal of the receiving circuit. The reason therefor is that the inputs of the receiving circuit connected to CANH and CANL are preceded by shunt resistors connecting CANH to ground and CANL to the positive voltage +5V, which constitutes the potential value of the high logic value. When line CANH is interrupted, the corresponding input terminal of the receiving circuit thus is connected to ground via the associated shunt resistor.
The related signal diagram in FIG. 8 shows that in this case the potential of CANH remains constant on a low value and CANH+Voffset thus remain on a correspondingly increased constant value. As the pulse signal of CANL still exceeds and then falls below the threshold value established by CANH+Voffset, a usable and correct pulse signal is still created at the output terminal RxD.
Case 3
When line CANL is interrupted, the corresponding input terminal of the receiving circuit is raised to +5V via the associated shunt resistor, and this voltage value is fed to the inverting input of comparator COMP1 in constant manner. This is shown in the signal diagram in FIG. 9. Due to the fact that the constant potential value of CANL in this case crosses the potential path CANH+Voffset, a pulse signal is created at output terminal RxD which contains the information of the pulse signal received via CANH and is only inverted with respect to the pulse signal on the output side which is obtained for cases 1 and 2.
Case 4
A short circuit of CANH towards a voltage of more than 5V is determined with the aid of comparator COMP2. The signal occurring at the output thereof during such determination effects via multiplex logic control circuit MUX switching over of the switching means SW to the output of comparator COMP5. The receiving circuit now operates in a single-line mode using the pulse signal arriving via CANL and deciding whether this pulse signal is greater or smaller than the reference voltage of 2.8V.
Case 5
When CANL is short circuited to ground, this results in a permanent dominant voltage level at output RxD, i.e., a voltage level that is permanently lower than the switching threshold value CANH+Voffset and thus the sum of the pulse signal voltage entering via CANH and the offset voltage. As the CAN protocol prescribes a logic value change of the pulse signals transferred at the latest after a predetermined period of time after beginning of the particular pulse., the condition that a logic value change no longer occurs at output RxD, constitutes a violation of the CAN protocol. For monitoring such a violation, timer T is provided. When the latter detects no logic value change at output RxD after a predetermined delay time, timer T via multiplex logic control circuit MUX effects switching over of switching means SW such that RxD is connected to the output of COMP4, so that as of this moment only a single-line operation takes place, evaluating the pulse signals arriving via CANH. Until the timer has responded and effected switching over to such single-line operation, data transferred, however, have been missed. It is thus necessary to retransfer these data from the transmitting point. This means that a certain amount of the data transmitted always has to be stored on the transmitter side in order to permit retransmitting to the receiving circuit in case of this error.
Case 6
A short circuit of CANH to ground leads to the same conditions and the same circuit diagram as shown in FIG. 8. This means that a correct data transfer still takes place in this case too.
Case 7
When CANL is short circuited towards the battery voltage, this is detected with the aid of COMP3, which via MUX results in switching over of switching means SW such that RxD is connected to the output of CON94. Single-line operation then takes place using the pulse signal received via CANH, which again renders possible a correct data transfer.
Case 8
A short circuit between CANH and CANL results in a permanent dominant state. This means, a logic value change no longer takes place at output RxD of the receiving circuit. As in case 5, this is determined by means of timer T. Due to the fact that this permanent dominant state is ascertained by the transmitter as well, switching over to single-line operation using CANH is effected on the transmitter side, while CANL is left open on the transmitter side and thus in a floating state in terms of potential. Due to the fact that the determination of this error takes place with a delay, a new data transfer has to be performed in this case as well, entailing the necessity to store the transmitted data for a predetermined period of time each.
The invention makes available a receiving circuit in which in error case 5, i.e., short circuit of line CANL to ground, no loss of data takes place when no data are stored on the transmitter side.
A receiving circuit according to the invention, with respect to comparators COMP2 to COMP5, multiplex control logic circuit MUX and switching means SW, has the same structure as the known circuit shown in FIG. 6. The receiving circuit according to the invention, in comparison with the known receiving circuit, has substantially the following differences:
1. Comparator circuit COMP1 of the known receiving circuit is replaced by a comparator circuit assembly superimposing on the pulse signal received via both lines both a positive and a negative offset voltage and having two comparator outputs. A first one of these comparator outputs delivers a first logic potential value when the pulse signal without offset superimposition exceeds a higher, first threshold value corresponding to the potential value of the other pulse signal increased by the positive offset voltage, and otherwise delivers a second logic potential value. The second comparator output delivers the first logic potential value when the pulse signal without offset superimposition exceeds a lower, second threshold value corresponding to the potential value of the other pulse signal reduced by the negative offset voltage, and otherwise delivers the second logic potential value.
2. Between this comparator circuit assembly and the signal output, there is connected a bistable multivibrator circuit which can be switched to a setting state by a change of the first and/or second comparator output to the first logic potential value, and which can be switched to a resetting state by a change of the first and/or second comparator output to the second logic potential value.
The circuit according to the invention, in cases 1 to 4 and 6 to 8, operates in the same manner as the known receiving circuit. A different mode of operation arises in case 5, i.e., in case of a short circuit of CANL to ground. In case of this error, the circuit according to the invention remains without delay and in proper operation so that no data loss can take place and no transmitted data need to be stored on the transmitter side in this error case, either.
In a preferred embodiment of the invention, the comparator circuit assembly provided in place of COMP1 of the known circuit, consists of two comparators having their inverting inputs connected directly to a fine of the double-fine bus and having their non-inverting inputs connected to the other line of the double-line bus via one offset voltage source each. Due to this design, both a positive and a negative offset voltage are superimposed on the pulse signal received via a line. Both comparators thus detect when the pulse signal without offset superimposition exceeds the higher, first threshold value and the lower, second threshold value, respectively.
A preferred embodiment of the invention uses as bistable multivibrator circuit a dynamic RS flip-flop having two setting inputs responsive to increasing edges and two resetting inputs responsive to decreasing edges. One of the two setting inputs and one of the two resetting inputs are each connected to the first comparator output, and the second setting input and the second resetting input are connected to the second comparator output.
Standard RS flip-flops with static inputs involve the disadvantage that the setting input and the resetting input must not be fed with setting-activating and, respectively, resetting-activating pulses which overlap in time. When the resetting input is fed with a pulse activating the same, before the pulse just activating the setting input has terminated, an undefined or not sensible mode of operation of such a flip-flop results.
According to a preferred embodiment of the invention, a dynamic RS flip-flop is used. With such flip-flops it is admissible to feed to the resetting input a pulse activating the same, before the pulse activating the setting input is over, or vice versa. Non-permissible states as with the static RS flip-flop do not exist in case of the dynamic RS flip-flop. Such a dynamic RS flip flop can be provided and operated with a plurality of setting inputs and with a plurality of resetting inputs.
Due to the fact that the evaluation of the two pulse signals arriving via the two lines by means of the two comparators of the comparator circuit assembly gives rise to overlapping of the pulses occurring at the outputs of both comparators, a static standard RS flip-flop would not be suitable for the bistable multivibrator circuit of the receiving circuit according to the invention. A bistable multivibrator circuit in the form of a dynamic RS flip-flop is therefore preferred.